1. Field of the Invention
The invention relates generally to memory controller logic and more specifically relates to improved structures and systems for voltage and temperature (VT) invariant, fast rank switching in control of DDR3 SDRAM devices.
2. Discussion of Related Art
In the control of synchronous dynamic random access memory (SDRAM) phase relationships between clock signals (CK) and strobe signals (DQS) indicating validity of an associated data signal (DQ) are important to proper operation of the SDRAM device. In particular, so-called “double data rate” (DDR) SDRAM devices require significant care in the design of memory controlling devices to assure proper alignment and timing of these various signals. In more recent DDR2 SDRAM devices, these signals are specified to much faster data rates and consequently timing tolerances became even more critical. In like manner, newer DDR3 data rate have again increased and thus the related timing tolerance are still tighter.
In the architecture of DDR3 memory control, a so-called “fly-by” architecture is proposed by the related specifications where the clock (CK) signal from a memory control device is serially daisy chained from SDRAM device to SDRAM device. So distributing the CK signal over the various SDRAM devices (i.e., over multiple ranks) results in an approximate 0 to 2 ns skew between the CK signal and the individual DQS (data strobe) signals applied to each rank. Such a skew can violate a requirement of DDR3 signal timing that requires a ¼ clock phase relationship between the CK signal and the DQS signal as applied to a particular rank.
With such a tight timing tolerance in view of the higher data rates of DDR3 standards, some technique must be employed to match individual DQS and DQ signals to corresponding CK signals. This problem is further exacerbated when multiple ranks of SDRAMs are provided. For example, in an application with two DDR3 SDRAM slots, each slot having 2 ranks, the cumulative delays of the fly-by clock over 4 such ranks of DDR3 SDRAM devices can violate the timing requirements of DDR3 standards.
Prior solutions to assure proper timing in DDR2 SDRAM application have relied on the fact that a DDR2 CK signal was matched to a corresponding DQS signal within the SDRAM package. If the skew of the CK and DQS signals was kept to a minimum within the memory control device and the associated PC board layout, then any difference of signal timing across the four ranks of SDRAM devices could be absorbed by the ¼ clock cycle tolerance allowed for CK and DQS skew. The higher data rates of DDR3 SDRAM standards and the fly-by architecture of the CK signal have rendered this older assumption invalid. An example of DDR3 fly-by CK architecture is shown in prior art FIG. 1. Two DIMMs (104 and 106) are configured in the exemplary prior art system 100 of FIG. 1. A CK signal 150 is generated by controller 102 and distributed in a fly-by layout (the thicker signal line). Associated DQ/DQS signals (120.0 through 120.8) are generated by controller 102 and distributed to associated SDRAM chips on each of four banks (110 through 113) of DIMM memory packages 104 and 106. With a DDR3 CK frequency of 800 MHz to 1.6 GHz, the ¼ cycle tolerance for CK to DQS skew is 312 ps, which is easily broken across a single group of four ranks (having a typical skew of 0.2 to 0.4 ns), let alone, the larger skew associated with the CK fly-by architecture (having a typical skew of 2 ns).
One prior solution to these timing skew problems of a DDR3 SDRAM fly-by clock architecture is to provide delay lines 160 within the controller 102 and to perform a so-called “write-leveling” procedure. The write-leveling procedure is a process to configure the use of the variable delay lines within the memory controller to adapt to the particular timing requirements of the SDRAM application. The write-leveling operation is performed at startup of the system using the DDR3 SDRAM subsystem. However, such delay lines may be subject to VT variation as the memory system is operable. Thus, for high reliability in high speed applications it may be necessary to periodically repeat the write-leveling operation. Since the write-leveling operation requires that the memory subsystem be “off-line” (e.g., unusable for its intended application function), such periodic repetition of write-leveling operations may degrade the performance of the system using the DDR3 SDRAM subsystem.
Thus it is an ongoing challenge to provide VT invariant DDR3 SDRAM applications that permit continuous high speed operation.